1. Field
Embodiments of the present inventive concepts relate to a method for fabricating a semiconductor device, and devices made thereby.
2. Description of the Background
As semiconductor devices have become more compact, higher-speed, and lower-voltage, planar semiconductor devices have begun to exhibit undesirable characteristics. For example, the short-channel effect increases “off-state” leakage current, which increase the power requirements of a device, even when it is not operating. In response to these problems and other problems associated with planar field effect transistors (FETs), non-planar, multi-gate devices have been developed. A multi-gate device employs a plurality of gates around a FET's channel to more effectively suppress “off-state” leakage current. Additionally, multiple gates afford greater drive current in the “on-state.” Lower “off-state” current and greater “on-state” current yields lower power consumption and greater drive performance for a multi-gate FET. Non-planar devices also offer the advantage of greater compactness. Non-planar multi-gate devices that employ a conducting channel wrapped in a “fin” of silicon may be referred to as FinFETs.
A gate-last process, may be used to form a FinFET. In such a process, a source region and a drain region are formed in an active fin of a FinFET on either side of an area where a gate is to be formed, followed by formation of a gate electrode (which may be, for example, a metal electrode).
In such a process, in order to form the source region and the drain region in the active fin, a dummy gate pattern may be formed on the active fin before forming the gate electrode. In general, such a dummy gate pattern may be formed by forming a dummy gate film on an upper portion of a substrate that includes a base and an active fin and then patterning the formed dummy gate film.
However, because the Fin FET is formed so that the active fin projects from the base, a stepped portion is formed while the dummy gate film is formed. Patterning a dummy gate film having a stepped portion (due to underlying an underlying fin) to form a dummy gate may preclude proper node separation between devices, with negative consequences for product reliability.